-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"

-- DATE "04/07/2021 16:15:28"

-- 
-- Device: Altera EP3C40F780C8 Package FBGA780
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY CYCLONEIII;
LIBRARY IEEE;
USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	fourplus2 IS
    PORT (
	S1 : OUT std_logic;
	a1 : IN std_logic;
	b1 : IN std_logic;
	Ci_1 : IN std_logic;
	S2 : OUT std_logic;
	a2 : IN std_logic;
	b2 : IN std_logic;
	S3 : OUT std_logic;
	a3 : IN std_logic;
	b3 : IN std_logic;
	S4 : OUT std_logic;
	a4 : IN std_logic;
	b4 : IN std_logic;
	CO_4 : OUT std_logic
	);
END fourplus2;

-- Design Ports Information
-- S1	=>  Location: PIN_Y6,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- S2	=>  Location: PIN_V1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- S3	=>  Location: PIN_AA7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- S4	=>  Location: PIN_T7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- CO_4	=>  Location: PIN_T9,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- Ci_1	=>  Location: PIN_AA8,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- a1	=>  Location: PIN_V3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- b1	=>  Location: PIN_AB7,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- a2	=>  Location: PIN_Y3,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- b2	=>  Location: PIN_W1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- a3	=>  Location: PIN_U6,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- b3	=>  Location: PIN_AC1,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- a4	=>  Location: PIN_AA6,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- b4	=>  Location: PIN_AE7,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF fourplus2 IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_S1 : std_logic;
SIGNAL ww_a1 : std_logic;
SIGNAL ww_b1 : std_logic;
SIGNAL ww_Ci_1 : std_logic;
SIGNAL ww_S2 : std_logic;
SIGNAL ww_a2 : std_logic;
SIGNAL ww_b2 : std_logic;
SIGNAL ww_S3 : std_logic;
SIGNAL ww_a3 : std_logic;
SIGNAL ww_b3 : std_logic;
SIGNAL ww_S4 : std_logic;
SIGNAL ww_a4 : std_logic;
SIGNAL ww_b4 : std_logic;
SIGNAL ww_CO_4 : std_logic;
SIGNAL \S1~output_o\ : std_logic;
SIGNAL \S2~output_o\ : std_logic;
SIGNAL \S3~output_o\ : std_logic;
SIGNAL \S4~output_o\ : std_logic;
SIGNAL \CO_4~output_o\ : std_logic;
SIGNAL \Ci_1~input_o\ : std_logic;
SIGNAL \b1~input_o\ : std_logic;
SIGNAL \a1~input_o\ : std_logic;
SIGNAL \inst|Add1~0_combout\ : std_logic;
SIGNAL \b2~input_o\ : std_logic;
SIGNAL \a2~input_o\ : std_logic;
SIGNAL \inst|Add1~1_combout\ : std_logic;
SIGNAL \inst2|Add1~0_combout\ : std_logic;
SIGNAL \b3~input_o\ : std_logic;
SIGNAL \a3~input_o\ : std_logic;
SIGNAL \inst3|Add0~0_combout\ : std_logic;
SIGNAL \inst3|Add1~0_combout\ : std_logic;
SIGNAL \a4~input_o\ : std_logic;
SIGNAL \b4~input_o\ : std_logic;
SIGNAL \inst3|Add1~1_combout\ : std_logic;
SIGNAL \inst3|Add1~2_combout\ : std_logic;
SIGNAL \inst4|Add1~0_combout\ : std_logic;
SIGNAL \inst4|Add1~1_combout\ : std_logic;

BEGIN

S1 <= ww_S1;
ww_a1 <= a1;
ww_b1 <= b1;
ww_Ci_1 <= Ci_1;
S2 <= ww_S2;
ww_a2 <= a2;
ww_b2 <= b2;
S3 <= ww_S3;
ww_a3 <= a3;
ww_b3 <= b3;
S4 <= ww_S4;
ww_a4 <= a4;
ww_b4 <= b4;
CO_4 <= ww_CO_4;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

-- Location: IOOBUF_X0_Y13_N9
\S1~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst|Add1~0_combout\,
	devoe => ww_devoe,
	o => \S1~output_o\);

-- Location: IOOBUF_X0_Y15_N9
\S2~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst2|Add1~0_combout\,
	devoe => ww_devoe,
	o => \S2~output_o\);

-- Location: IOOBUF_X0_Y12_N2
\S3~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst3|Add1~0_combout\,
	devoe => ww_devoe,
	o => \S3~output_o\);

-- Location: IOOBUF_X0_Y12_N16
\S4~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst4|Add1~0_combout\,
	devoe => ww_devoe,
	o => \S4~output_o\);

-- Location: IOOBUF_X0_Y11_N23
\CO_4~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \inst4|Add1~1_combout\,
	devoe => ww_devoe,
	o => \CO_4~output_o\);

-- Location: IOIBUF_X0_Y12_N22
\Ci_1~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_Ci_1,
	o => \Ci_1~input_o\);

-- Location: IOIBUF_X0_Y8_N15
\b1~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_b1,
	o => \b1~input_o\);

-- Location: IOIBUF_X0_Y16_N1
\a1~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_a1,
	o => \a1~input_o\);

-- Location: LCCOMB_X1_Y12_N0
\inst|Add1~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst|Add1~0_combout\ = \Ci_1~input_o\ $ (\b1~input_o\ $ (\a1~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \Ci_1~input_o\,
	datac => \b1~input_o\,
	datad => \a1~input_o\,
	combout => \inst|Add1~0_combout\);

-- Location: IOIBUF_X0_Y15_N22
\b2~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_b2,
	o => \b2~input_o\);

-- Location: IOIBUF_X0_Y11_N15
\a2~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_a2,
	o => \a2~input_o\);

-- Location: LCCOMB_X1_Y12_N26
\inst|Add1~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst|Add1~1_combout\ = (\Ci_1~input_o\ & ((\b1~input_o\) # (\a1~input_o\))) # (!\Ci_1~input_o\ & (\b1~input_o\ & \a1~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110011000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \Ci_1~input_o\,
	datac => \b1~input_o\,
	datad => \a1~input_o\,
	combout => \inst|Add1~1_combout\);

-- Location: LCCOMB_X1_Y12_N4
\inst2|Add1~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst2|Add1~0_combout\ = \b2~input_o\ $ (\a2~input_o\ $ (\inst|Add1~1_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1001011010010110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \b2~input_o\,
	datab => \a2~input_o\,
	datac => \inst|Add1~1_combout\,
	combout => \inst2|Add1~0_combout\);

-- Location: IOIBUF_X0_Y10_N15
\b3~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_b3,
	o => \b3~input_o\);

-- Location: IOIBUF_X0_Y13_N22
\a3~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_a3,
	o => \a3~input_o\);

-- Location: LCCOMB_X1_Y12_N6
\inst3|Add0~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|Add0~0_combout\ = \b3~input_o\ $ (\a3~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \b3~input_o\,
	datac => \a3~input_o\,
	combout => \inst3|Add0~0_combout\);

-- Location: LCCOMB_X1_Y12_N16
\inst3|Add1~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|Add1~0_combout\ = \inst3|Add0~0_combout\ $ (((\b2~input_o\ & ((\a2~input_o\) # (\inst|Add1~1_combout\))) # (!\b2~input_o\ & (\a2~input_o\ & \inst|Add1~1_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0001011111101000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \b2~input_o\,
	datab => \a2~input_o\,
	datac => \inst|Add1~1_combout\,
	datad => \inst3|Add0~0_combout\,
	combout => \inst3|Add1~0_combout\);

-- Location: IOIBUF_X0_Y12_N8
\a4~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_a4,
	o => \a4~input_o\);

-- Location: IOIBUF_X5_Y0_N29
\b4~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_b4,
	o => \b4~input_o\);

-- Location: LCCOMB_X1_Y12_N2
\inst3|Add1~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|Add1~1_combout\ = (\inst3|Add0~0_combout\ & ((\b2~input_o\ & ((\a2~input_o\) # (\inst|Add1~1_combout\))) # (!\b2~input_o\ & (\a2~input_o\ & \inst|Add1~1_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110100000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \b2~input_o\,
	datab => \a2~input_o\,
	datac => \inst|Add1~1_combout\,
	datad => \inst3|Add0~0_combout\,
	combout => \inst3|Add1~1_combout\);

-- Location: LCCOMB_X1_Y12_N12
\inst3|Add1~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst3|Add1~2_combout\ = (\inst3|Add1~1_combout\) # ((\b3~input_o\ & \a3~input_o\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111110100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \b3~input_o\,
	datac => \a3~input_o\,
	datad => \inst3|Add1~1_combout\,
	combout => \inst3|Add1~2_combout\);

-- Location: LCCOMB_X1_Y12_N14
\inst4|Add1~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst4|Add1~0_combout\ = \a4~input_o\ $ (\b4~input_o\ $ (\inst3|Add1~2_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010101011010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \a4~input_o\,
	datac => \b4~input_o\,
	datad => \inst3|Add1~2_combout\,
	combout => \inst4|Add1~0_combout\);

-- Location: LCCOMB_X1_Y12_N24
\inst4|Add1~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \inst4|Add1~1_combout\ = (\a4~input_o\ & ((\b4~input_o\) # (\inst3|Add1~2_combout\))) # (!\a4~input_o\ & (\b4~input_o\ & \inst3|Add1~2_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \a4~input_o\,
	datac => \b4~input_o\,
	datad => \inst3|Add1~2_combout\,
	combout => \inst4|Add1~1_combout\);

ww_S1 <= \S1~output_o\;

ww_S2 <= \S2~output_o\;

ww_S3 <= \S3~output_o\;

ww_S4 <= \S4~output_o\;

ww_CO_4 <= \CO_4~output_o\;
END structure;


